In its most elementary form, level sensitive scan design principles involve the use of a dedicated serial data path from an input pad to the serial inputs of concatenated LSSD shift registers for the purpose of scanning in test data which is then output during a testing interval to embedded logic on the integrated circuit chip to be tested. During the testing interval, the embedded logic processes the test data input from the LSSD scan string and outputs the result of that logical processing to an output LSSD shift register associated with the embedded logic. That output LSSD shift register then serially outputs the test result data to the same or to another LSSD scan string, which result data is serially output from the chip for test result analysis. These principles are described in greater detail in many of the following related patents:
U.S. Pat. No. 3,761,695 entitled "Method of Level Sensitive Testing a Functional Logic System," to Edward B. Eichelberger and of common assignee.
U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System," to Edward B. Eichelberger and of common assignee.
U.S. Pat. No. 3,806,891 entitled "Logic Circuit for Scan-In/Scan-Out," to Edward B. Eichelberger, Richard N. Gustafson and Clark Kurtz, and of common assignee.
U.S. Pat. No. 4,071,902 entitled "Reduced Overhead for Clock Testing in a Level System Scan Design (LSD) System," to Edward B. Eichelberger and Thomas W. Williams and assigned to the common assignee.